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5 (1)
7.1A CMOS circuit was designed based on company XYZ’s 3-
shown in Fig. P7.1 with WN = 1.2
(a) Determine the circuit configuration and draw the circuit diagram.
(b) For simple hand analysis, make the following assumptions:
i) Wiring parasitic capacitances and resistances are negligible.
ii) Device parameters are
nMOS pMOS
VT00.53 V –0.51 V
tox16 Å 18 Å
k'98.2
Xj32nm 32nm
LD10nm 10nm
ECL0.4V1.8V
iii) The total capacitance at node I is 0.1 pF.
iv) An ideal step-pulse signal is applied to the CK terminal such that
VCK = 1.2 V,t < 0
VCK = 0 V,0 ≤ t < Tw
VCK = 1.2 V, t ≥ Tw
VDD = 1.2 V
v) At t = 0, the node voltage at I is zero.
vi) The input voltages at A1, B1, and B2 are zero for 0 ≤ t ≤ TW.
Find the minimum TW that allows VI to reach 0.6 V.
Figure P7.1
7.1A CMOS circuit was designed based on company XYZ’s 3-
shown in Fig. P7.1 with WN = 1.2
(a) Determine the circuit configuration and draw the circuit diagram.
(b) For simple hand analysis, make the following assumptions:
i) Wiring parasitic capacitances and resistances are negligible.
ii) Device parameters are
nMOS pMOS
VT00.53 V –0.51 V
tox16 Å 18 Å
k'98.2
Xj32nm 32nm
LD10nm 10nm
ECL0.4V1.8V
iii) The total capacitance at node I is 0.1 pF.
iv) An ideal step-pulse signal is applied to the CK terminal such that
VCK = 1.2 V,t < 0
VCK = 0 V,0 ≤ t < Tw
VCK = 1.2 V, t ≥ Tw
VDD = 1.2 V
v) At t = 0, the node voltage at I is zero.
vi) The input voltages at A1, B1, and B2 are zero for 0 ≤ t ≤ TW.
Find the minimum TW that allows VI to reach 0.6 V.
Figure P7.1
SOLUTION :
(a)
(b)
In PMOS
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