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Solution for CMOS Digital Integrated Circuits Analysis and Design 3RD Edition Chapter 6, Problem 10

by Sung-Mo, Kang and Yusuf Leblebici
77 Solutions 13 Chapters 25311 Studied ISBN: 9780072460537 Electrical Engineering 5 (1)

Chapter 6, Problem Exercise_Problems 10 :   6.10 Consider a CMOS inverter...

 

6.10 Consider a CMOS inverter with the following parameters:

 

VT0,n = 0.5 VnCox = 98 A/V2(W/L)n = 20

VT0,p = - 0.48 VpCox = 46 A/V2(W/L)p = 30

The power suply voltage is 1.2 V, and the output load capacitance is 10 fF.

(a)Calculate the rise time and the fall time of the output signal using the exact method (differential equation) and average current method.

6.10 Consider a CMOS inverter with the following parameters:

 

VT0,n = 0.5 VnCox = 98 A/V2(W/L)n = 20

VT0,p = - 0.48 VpCox = 46 A/V2(W/L)p = 30

The power suply voltage is 1.2 V, and the output load capacitance is 10 fF.

(b)Determine the maximum frequency of a periodic square-wave input signal so

that the output voltage can still exhibit a full logic swing from 0 to 1.2 V in

each cycle.

(c)Calculate the dynamic power dissipation at this frequency.

(d)Assume that the output load capacitance is mainly dominated by fixed fan-

out components (which are independent of Wn and Wp). We want to re-design the inverter so that the propagation delay times are reduced by 25%. Determine the required channel dimensions of the nMOS and the pMOS transistors. How does this re-design influence the switching (inversion) threshold?

 

 

Step-By-Step Solution

Chapter 6, Problem Exercise_Problems 10

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