## Solution for CMOS Digital Integrated Circuits Analysis and Design 3RD Edition Chapter 4, Problem 1

by Sung-Mo, Kang and Yusuf Leblebici
77 Solutions 13 Chapters 24436 Studied ISBN: 9780072460537 5 (1)

# Chapter 4, Problem Exercise_Problems 1 : 4.1Rewrite the SPICE code for the nMOS model...

4.1Rewrite the SPICE code for the nMOS model in Example 4.1 for agraded junction

using the following parameters:

NA = 9.60×1018 cm-3

NA (sidewall) = 7.46×1015 cm-3

ND = 4.80 ×1017cm-3

xj = 0.02μm

tox = 6Å

LD = 4 nm

## Step-By-Step Solution

4.1Rewrite the SPICE code for the nMOS model in Example 4.1 for agraded junction

using the following parameters:

NA = 9.60×1018 cm-3

NA (sidewall) = 7.46×1015 cm-3

ND = 4.80 ×1017cm-3

xj = 0.02μm

tox = 6Å

LD = 4 nm

SOLUTION :

The zero-bias threshold voltage is measured as 0.53V, and k is determined to 98.2 uA/V2. The channel length modulation coefficient is λ=0.08. The source, drain, gate, and substrate nodes of the device are labeled by node numbers 4, 6, 12, and 7, respectively. Prepare the device description line and the .MODEL line for SPICE simulation. Use the LEVEL 1 model, and avoid conflicting parameter definitions.

The gate oxide capacitance per unit area is

The substrate bias coefficient (GAMMA) and the surface inversion potential (PHI) are found as follows:

Now we start to calculate the parameters needed for the parasitic capacitance descriptions. The built-in junction potential (PB) for the bottom diffusion area is

Note that this junction potential is used for calculating alljunction capacitances, which results in an overestimation of the sidewall junction capacitance. The zero-bias depletion capacitances associated with the bottom junction (CJ) and the side-wall junction (CJSW) are found as

We will assume abrupt junction profiles for both the bottom junctions and the side-wall junctions; thus, MJ = 0.5 and MJSW = 0.33. The gate overlap capacitances per unit length (CGSO and CGDO) are calculated as:

Finally, we calculate the area and the perimeter (in m2 and m, respectively) of the source and the drain diffusion regions. Now, we can write the device description line and the .MODEL line that correspond to this device, as follows:

M1 6 12 4 7 NM1 W=200N L=120NLD=10NAS=0.058P PS=0.98U AD=0.1492P PD=1.7U

.MODEL NM1 NMOS (VTO=0.53KP=98.2U LAMBDA=0.08GAMMA=0.306

+                   PHI=1.06 PB=0.978 CJ=1.97E-3 CJSW=5.00E-12

+                   CGSO=2.34E-10 CGDO=2.34E-10 MJ=0.5 MJSW=0.33)

Notice that PS and PD are calculated here by taking into account the entire perimeter of the respective diffusion region, including the boundaries facing the gate (channel). Similarly, AS and AD are simply taken as the bottom area of the respective diffusion region. This approach slightly diverges from the exact capacitance calculation formulas given in Chapter 3, and results in a minor over-estimation of the actual junction capacitances. Yet due to the relative simplicity of calculating the area and the perimeter of polygons (i.e., source and drain regions) defined in the mask layout, this method can easily be applied to automatic layout parasitic extraction.