## Solution for CMOS Digital Integrated Circuits Analysis and Design 3RD Edition Chapter 13, Problem 1

by Sung-Mo, Kang and Yusuf Leblebici
77 Solutions 13 Chapters 24440 Studied ISBN: 9780072460537 5 (1)

# Chapter 13, Problem Exercise_Problems 1 : 13.1For low-power design, multiple power supply voltages may...

13.1For low-power design, multiple power supply voltages may be used on a chipby using on-chip voltage converters. A chip may take in a 5.0-V power supply and then in turn generate and use 3.3-V power rails besides 5.0-V power rails. Design a level shifter thatcan interface 3.3-V logic with a 5.0-V logic circuit. Use |VT0| = 1.0 Vnp = 3 in your calculation.

## Step-By-Step Solution

13.1For low-power design, multiple power supply voltages may be used on a chipby using on-chip voltage converters. A chip may take in a 5.0-V power supply and then in turn generate and use 3.3-V power rails besides 5.0-V power rails. Design a level shifter thatcan interface 3.3-V logic with a 5.0-V logic circuit. Use |VT0| = 1.0 Vnp = 3 in your calculation.

SOLUTION:

The worst case output signal levels are:

Therefore the inverter threshold voltage should be set at 1.65V.

From equation(13.4),assume channel lengths are the same for both pMOS and nMOS.